Repositori institucional URV
| URV's Author/s: | Cantó Navarro, Enrique Fernando |
| Author, as appears in the article.: | Navarro EC; Lara RR; García ML |
| Author's mail: | enrique.canto@urv.cat |
| Author identifier: | 0000-0002-5674-4119 |
| Journal publication year: | 2022 |
| Publication Type: | Journal Publications |
| APA: | Navarro EC; Lara RR; García ML (2022). Online Signature Verification Systems on a Low-Cost FPGA. Applied Sciences-Basel, 12(1), -. DOI: 10.3390/app12010378 |
| Papper original source: | Applied Sciences-Basel. 12 (1): |
| Abstract: | This paper describes three different approaches for the implementation of an online signature verification system on a low-cost FPGA. The system is based on an algorithm, which operates on real numbers using the double-precision floating-point IEEE 754 format. The double-precision computations are replaced by simpler formats, without affecting the biometrics performance, in order to permit efficient implementations on low-cost FPGA families. The first approach is an embedded system based on MicroBlaze, a 32-bit soft-core microprocessor designed for Xilinx FPGAs, which can be configured by including a single-precision floating-point unit (FPU). The second implementation attaches a hardware accelerator to the embedded system to reduce the execution time on floating-point vectors. The last approach is a custom computing system, which is built from a large set of arithmetic circuits that replace the floating-point data with a more efficient representation based on fixed-point format. The latter system provides a very high runtime acceleration factor at the expense of using a large number of FPGA resources, a complex development cycle and no flexibility since it cannot be adapted to other biometric algorithms. By contrast, the first system provides just the opposite features, while the second approach is a mixed solution between both of them. The experimental results show that both the hardware accelerator and the custom computing system reduce the execution time by a factor ×7.6 and ×201 but increase the logic FPGA resources by a factor ×2.3 and ×5.2, respectively, in comparison with the MicroBlaze embedded system. |
| Article's DOI: | 10.3390/app12010378 |
| Link to the original source: | https://www.mdpi.com/2076-3417/12/1/378 |
| Papper version: | info:eu-repo/semantics/publishedVersion |
| licence for use: | https://creativecommons.org/licenses/by/3.0/es/ |
| Department: | Enginyeria Electrònica, Elèctrica i Automàtica |
| Licence document URL: | https://repositori.urv.cat/ca/proteccio-de-dades/ |
| Thematic Areas: | Química Process chemistry and technology Physics, applied Materials science, multidisciplinary Materials science (miscellaneous) Materials science (all) Materiais Instrumentation General materials science General engineering Fluid flow and transfer processes Engineering, multidisciplinary Engineering (miscellaneous) Engineering (all) Engenharias ii Engenharias i Computer science applications Ciências biológicas iii Ciências biológicas ii Ciências biológicas i Ciências agrárias i Ciência de alimentos Chemistry, multidisciplinary Biodiversidade Astronomia / física |
| Keywords: | Recognition Online signature Hardware accelerator Fpga Fixed-point Dtw Biometrics verification hardware accelerator fpga fixed-point dtw biometrics verification |
| Entity: | Universitat Rovira i Virgili |
| Record's date: | 2024-09-07 |
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