Autor segons l'article: Lumbiarres-Lopez, Ruben; Lopez-Garcia, Mariano; Canto-Navarro, Enrique;
Departament: Enginyeria Electrònica, Elèctrica i Automàtica
Autor/s de la URV: Cantó Navarro, Enrique Fernando
Paraules clau: Software-hardware countermeasures Side-channel attacks Security Power analysis attacks
Resum: This paper presents a new hardware architecture designed for protecting the key of cryptographic algorithms against attacks by side-channel analysis (SCA). Unlike previous approaches already published, the fortress of the proposed architecture is based on revealing a false key. Such a false key is obtained when the leakage information, related to either the power consumption or the electromagnetic radiation (EM) emitted by the hardware device, is analysed by means of a classical statistical method. In fact, the trace of power consumption (or the EM) does not reveal any significant sign of protection in its behaviour or shape. Experimental results were obtained by using a Virtex 5 FPGA, on which a 128-bit version of the standard AES encryption algorithm was implemented. The architecture could easily be extrapolated to an ASIC device based on standard cell libraries. The system is capable of concealing the real key when various attacks are performed on the AES algorithm, using two statistical methods which are based on correlation, the Welch's t-test and the difference of means.
Àrees temàtiques: General computer science Engenharias iv Engenharias iii Electrical and electronic engineering Computer science, software engineering Computer science, information systems Computer science, hardware & architecture Computer science (miscellaneous) Computer science (all) Ciência da computação
Accès a la llicència d'ús: https://creativecommons.org/licenses/by/3.0/es/
Adreça de correu electrònic de l'autor: enrique.canto@urv.cat
Identificador de l'autor: 0000-0002-5674-4119
Data d'alta del registre: 2024-09-07
Versió de l'article dipositat: info:eu-repo/semantics/acceptedVersion
Enllaç font original: https://ieeexplore.ieee.org/document/7571149
URL Document de llicència: https://repositori.urv.cat/ca/proteccio-de-dades/
Referència a l'article segons font original: Ieee Transactions On Dependable And Secure Computing. 15 (5): 898-905
Referència de l'ítem segons les normes APA: Lumbiarres-Lopez, Ruben; Lopez-Garcia, Mariano; Canto-Navarro, Enrique; (2018). Hardware architecture implemented on FPGA for protecting cryptographic keys against side-channel attacks. Ieee Transactions On Dependable And Secure Computing, 15(5), 898-905. DOI: 10.1109/TDSC.2016.2610966
DOI de l'article: 10.1109/TDSC.2016.2610966
Entitat: Universitat Rovira i Virgili
Any de publicació de la revista: 2018
Tipus de publicació: Journal Publications