Repositori URV

Autor segons l'article: Espitia Castillo JD; Cantó Navarro E; Vidal-Idiarte E

Departament: Enginyeria Electrònica, Elèctrica i Automàtica

Autor/s de la URV: Cantó Navarro, Enrique Fernando / Espitia Castillo, Juan David / Vidal Idiarte, Enric

Paraules clau: Successive approximation register (sar) Pwm Lpf Interleaved sar adc Fpga Analog-to-digital converter (adc) successive approximation register (sar) pwm lpf fpga conversion

Resum: The flexibility provided by FPGAs permits the implementation of several ADCs, each one configured with the required bit resolution and sampling frequency. The paper presents the design and implementation of scalable and parametrizable analog-to-digital converters (ADC), based on a successive approximation register (SAR), on FPGAs (field programmable gate arrays). Firstly, the work develops a systematic methodology for the implementation of a parametrizable SAR-based ADC from a set of building modules, such as the pulse-width modulator (PWM), external low-pass filter (LPF) and the analog comparator. The presented method allows choosing the LPF parameters for the required performance (resolution bits and sampling frequency) of a SAR-based ADC. Secondly, the paper also presents several optimizations on the PWM module to enhance the sampling frequency of implemented ADCs, and the method to choose the LPF parameters is adapted. The PWM and SAR logic are synthesizable and parametrizable, using a low number of resources, in order to be portable for low-cost FPGA families. The methodology and PWM optimizations are tested on a Zynq-7000 device from Xilinx; however, they can be adapted to any other FPGA.

Àrees temàtiques: Signal processing Physics, applied Hardware and architecture Engineering, electrical & electronic Engenharias iv Electrical and electronic engineering Control and systems engineering Computer science, information systems Computer networks and communications

Accès a la llicència d'ús: https://creativecommons.org/licenses/by/3.0/es/

Adreça de correu electrònic de l'autor: enrique.canto@urv.cat enric.vidal@urv.cat juandavid.espitia@estudiants.urv.cat

Identificador de l'autor: 0000-0002-5674-4119 0000-0002-6016-4096

Data d'alta del registre: 2023-12-16

Versió de l'article dipositat: info:eu-repo/semantics/publishedVersion

Enllaç font original: https://www.mdpi.com/2079-9292/11/3/447

URL Document de llicència: http://repositori.urv.cat/ca/proteccio-de-dades/

Referència a l'article segons font original: Electronics. 11 (3):

Referència de l'ítem segons les normes APA: Espitia Castillo JD; Cantó Navarro E; Vidal-Idiarte E (2022). Design and Implementation of Scalable and Parametrizable Analog-to-Digital Converter on FPGA. Electronics, 11(3), -. DOI: 10.3390/electronics11030447

DOI de l'article: 10.3390/electronics11030447

Entitat: Universitat Rovira i Virgili

Any de publicació de la revista: 2022

Tipus de publicació: Journal Publications