Articles producció científicaEnginyeria Informàtica i Matemàtiques

A Security Model for Randomization-based Protected Caches

  • Dades identificatives

    Identificador:  imarina:9280516
    Autors:  Ribes-González J; Farràs O; Hernández C; Kostalabros V; Moretó M
    Resum:
    Cache side-channel attacks allow adversaries to learn sensitive information about co-running processes by using only access latency measures and cache contention. This vulnerability has been shown to lead to several microarchitectural attacks. As a promising solution, recent work proposes Randomization-based Protected Caches (RPCs). RPCs randomize cache addresses, changing keys periodically so as to avoid long-term leakage. Unfortunately, recent attacks have called the security of state-of-the-art RPCs into question. In this work, we tackle the problem of formally defining and analyzing the security properties of RPCs. We first give security definitions against access-based cache side-channel attacks that capture security against known attacks such as Prime+Probe and Evict+Probe. Then, using these definitions, we obtain results that allow to guarantee security by adequately choosing the rekeying period, the key generation algorithm and the cache randomizer, thus providing security proofs for RPCs under certain assumptions.
  • Altres:

    Enllaç font original: https://tches.iacr.org/index.php/TCHES/article/view/9693
    Referència de l'ítem segons les normes APA: Ribes-González J; Farràs O; Hernández C; Kostalabros V; Moretó M (2022). A Security Model for Randomization-based Protected Caches. Iacr Transactions On Cryptographic Hardware And Embedded Systems, 2022(3), 1-25. DOI: 10.46586/tches.v2022.i3.1-25
    Referència a l'article segons font original: Iacr Transactions On Cryptographic Hardware And Embedded Systems. 2022 (3): 1-25
    DOI de l'article: 10.46586/tches.v2022.i3.1-25
    Any de publicació de la revista: 2022
    Entitat: Universitat Rovira i Virgili
    Versió de l'article dipositat: info:eu-repo/semantics/publishedVersion
    Data d'alta del registre: 2024-09-07
    Autor/s de la URV: Farràs Ventura, Oriol / Ribes Gonzalez, Jordi
    Departament: Enginyeria Informàtica i Matemàtiques
    URL Document de llicència: https://repositori.urv.cat/ca/proteccio-de-dades/
    Tipus de publicació: Journal Publications
    Autor segons l'article: Ribes-González J; Farràs O; Hernández C; Kostalabros V; Moretó M
    Accès a la llicència d'ús: https://creativecommons.org/licenses/by/3.0/es/
    Àrees temàtiques: Software, Signal processing, Hardware and architecture, Computer networks and communications, Computer graphics and computer-aided design, Artificial intelligence
    Adreça de correu electrònic de l'autor: oriol.farras@urv.cat
  • Paraules clau:

    Timing attacks
    Security definition
    Randomly-mapped caches
    Randomization-based protected caches
    Pseudo-random functions
    Cache side-channel attacks
    Artificial Intelligence
    Computer Graphics and Computer-Aided Design
    Computer Networks and Communications
    Hardware and Architecture
    Signal Processing
    Software
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