Articles producció científica> Enginyeria Electrònica, Elèctrica i Automàtica

A new countermeasure against side-channel attacks based on hardware-software co-design

  • Dades identificatives

    Identificador: imarina:9285506
    Autors:
    Lumbiarres-Lopez RLopez-Garcia MCanto-Navarro E
    Resum:
    This paper aims at presenting a new countermeasure against Side-Channel Analysis (SCA) attacks, whose implementation is based on a hardware-software co-design. The hardware architecture consists of a microprocessor, which executes the algorithm using a false key, and a coprocessor that performs several operations that are necessary to retrieve the original text that was encrypted with the real key. The coprocessor hardly affects the power consumption of the device, so that any classical attack based on such power consumption would reveal a false key. Additionally, as the operations carried out by the coprocessor are performed in parallel with the microprocessor, the execution time devoted for encrypting a specific text is not affected by the proposed countermeasure. In order to verify the correctness of our proposal, the system was implemented on a Virtex 5 FPGA. Different SCA attacks were performed on several functions of AES algorithm. Experimental results show in all cases that the system is effectively protected by revealing a false encryption key. © 2016
  • Altres:

    Autor segons l'article: Lumbiarres-Lopez R; Lopez-Garcia M; Canto-Navarro E
    Departament: Enginyeria Electrònica, Elèctrica i Automàtica
    Autor/s de la URV: Cantó Navarro, Enrique Fernando
    Paraules clau: Virtex-5 Software design Side-channel analysis Side channel attack Reconfigurable hardware Integrated circuit design Hardware-software codesign Hardware architecture Hardware Encryption key Electric power utilization Cryptography Countermeasure Co-processors Co-designs Aes algorithms Aes algorithm and hardware-software co-design
    Resum: This paper aims at presenting a new countermeasure against Side-Channel Analysis (SCA) attacks, whose implementation is based on a hardware-software co-design. The hardware architecture consists of a microprocessor, which executes the algorithm using a false key, and a coprocessor that performs several operations that are necessary to retrieve the original text that was encrypted with the real key. The coprocessor hardly affects the power consumption of the device, so that any classical attack based on such power consumption would reveal a false key. Additionally, as the operations carried out by the coprocessor are performed in parallel with the microprocessor, the execution time devoted for encrypting a specific text is not affected by the proposed countermeasure. In order to verify the correctness of our proposal, the system was implemented on a Virtex 5 FPGA. Different SCA attacks were performed on several functions of AES algorithm. Experimental results show in all cases that the system is effectively protected by revealing a false encryption key. © 2016
    Àrees temàtiques: Software Interdisciplinar Hardware and architecture Engineering, electrical & electronic Engenharias iv Engenharias iii Computer science, theory & methods Computer science, hardware & architecture Computer networks and communications Ciências biológicas i Ciência da computação Artificial intelligence
    Accès a la llicència d'ús: https://creativecommons.org/licenses/by/3.0/es/
    Adreça de correu electrònic de l'autor: enrique.canto@urv.cat
    Identificador de l'autor: 0000-0002-5674-4119
    Data d'alta del registre: 2024-09-07
    Versió de l'article dipositat: info:eu-repo/semantics/acceptedVersion
    Enllaç font original: https://www.sciencedirect.com/science/article/abs/pii/S014193311630076X
    URL Document de llicència: https://repositori.urv.cat/ca/proteccio-de-dades/
    Referència a l'article segons font original: Microprocessors And Microsystems. 45 324-338
    Referència de l'ítem segons les normes APA: Lumbiarres-Lopez R; Lopez-Garcia M; Canto-Navarro E (2016). A new countermeasure against side-channel attacks based on hardware-software co-design. Microprocessors And Microsystems, 45(), 324-338. DOI: 10.1016/j.micpro.2016.06.009
    DOI de l'article: 10.1016/j.micpro.2016.06.009
    Entitat: Universitat Rovira i Virgili
    Any de publicació de la revista: 2016
    Tipus de publicació: Journal Publications
  • Paraules clau:

    Artificial Intelligence,Computer Networks and Communications,Computer Science, Hardware & Architecture,Computer Science, Theory & Methods,Engineering, Electrical & Electronic,Hardware and Architecture,Software
    Virtex-5
    Software design
    Side-channel analysis
    Side channel attack
    Reconfigurable hardware
    Integrated circuit design
    Hardware-software codesign
    Hardware architecture
    Hardware
    Encryption key
    Electric power utilization
    Cryptography
    Countermeasure
    Co-processors
    Co-designs
    Aes algorithms
    Aes algorithm and hardware-software co-design
    Software
    Interdisciplinar
    Hardware and architecture
    Engineering, electrical & electronic
    Engenharias iv
    Engenharias iii
    Computer science, theory & methods
    Computer science, hardware & architecture
    Computer networks and communications
    Ciências biológicas i
    Ciência da computação
    Artificial intelligence
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