Articles producció científica> Enginyeria Informàtica i Matemàtiques

Replacement techniques for dynamic NUCA cache designs on CMPs

  • Identification data

    Identifier: PC:250
    Handle: https://hdl.handle.net/20.500.11797/PC250
    Authors:
    González, A.Rakvic, R.Molina, C.Lira. J.
    Abstract:
    10.1007/s11227-012-0859-6

  • Others:

    Author, as appears in the article.: González, A. Rakvic, R. Molina, C. Lira. J.
    Papper version: info:eu-repo/semantics/submittedVersion
    Department: Enginyeria Informàtica i Matemàtiques
    Licence document URL: https://repositori.urv.cat/ca/proteccio-de-dades/
    Abstract: The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have been proposed to address this problem. Furthermore, an efficient last-level cache is crucial in chip multiprocessors (CMP) architectures to reduce requests to the offchip memory, because of the significant speed gap between processor and memory. Therefore, a bank replacement policy that efficiently manages the NUCA cache is desirable. However, the decentralized nature of NUCA has eliminated the effectiveness of replacement policies because banks operate independently of each other, and hence their replacement decisions are restricted to a single NUCA bank. In this paper, we propose three different techniques to deal with replacements in NUCA caches.
    Entity: Universitat Rovira i Virgili.
    Journal publication year: 2013
    licence for use: https://creativecommons.org/licenses/by/3.0/es/
    ISSN: 0920-8542
    First page: 548
    Last page: 579
    Journal volume: 64