Author, as appears in the article.: Lumbiarres-Lopez, Ruben; Lopez-Garcia, Mariano; Canto-Navarro, Enrique;
Department: Enginyeria Electrònica, Elèctrica i Automàtica
URV's Author/s: Cantó Navarro, Enrique Fernando
Keywords: Software-hardware countermeasures Side-channel attacks Security Power analysis attacks
Abstract: This paper presents a new hardware architecture designed for protecting the key of cryptographic algorithms against attacks by side-channel analysis (SCA). Unlike previous approaches already published, the fortress of the proposed architecture is based on revealing a false key. Such a false key is obtained when the leakage information, related to either the power consumption or the electromagnetic radiation (EM) emitted by the hardware device, is analysed by means of a classical statistical method. In fact, the trace of power consumption (or the EM) does not reveal any significant sign of protection in its behaviour or shape. Experimental results were obtained by using a Virtex 5 FPGA, on which a 128-bit version of the standard AES encryption algorithm was implemented. The architecture could easily be extrapolated to an ASIC device based on standard cell libraries. The system is capable of concealing the real key when various attacks are performed on the AES algorithm, using two statistical methods which are based on correlation, the Welch's t-test and the difference of means.
Thematic Areas: General computer science Engenharias iv Engenharias iii Electrical and electronic engineering Computer science, software engineering Computer science, information systems Computer science, hardware & architecture Computer science (miscellaneous) Computer science (all) Ciência da computação
licence for use: https://creativecommons.org/licenses/by/3.0/es/
Author's mail: enrique.canto@urv.cat
Author identifier: 0000-0002-5674-4119
Record's date: 2024-09-07
Papper version: info:eu-repo/semantics/acceptedVersion
Link to the original source: https://ieeexplore.ieee.org/document/7571149
Licence document URL: https://repositori.urv.cat/ca/proteccio-de-dades/
Papper original source: Ieee Transactions On Dependable And Secure Computing. 15 (5): 898-905
APA: Lumbiarres-Lopez, Ruben; Lopez-Garcia, Mariano; Canto-Navarro, Enrique; (2018). Hardware architecture implemented on FPGA for protecting cryptographic keys against side-channel attacks. Ieee Transactions On Dependable And Secure Computing, 15(5), 898-905. DOI: 10.1109/TDSC.2016.2610966
Article's DOI: 10.1109/TDSC.2016.2610966
Entity: Universitat Rovira i Virgili
Journal publication year: 2018
Publication Type: Journal Publications
Repositori URV