Articles producció científica> Enginyeria Electrònica, Elèctrica i Automàtica

Design and Implementation of Scalable and Parametrizable Analog-to-Digital Converter on FPGA

  • Identification data

    Identifier: imarina:9244546
  • Authors:

    Espitia Castillo JD
    Cantó Navarro E
    Vidal-Idiarte E
  • Others:

    Author, as appears in the article.: Espitia Castillo JD; Cantó Navarro E; Vidal-Idiarte E
    Department: Enginyeria Electrònica, Elèctrica i Automàtica
    URV's Author/s: Cantó Navarro, Enrique Fernando / Espitia Castillo, Juan David / Vidal Idiarte, Enric
    Keywords: Successive approximation register (sar) Pwm Lpf Interleaved sar adc Fpga Analog-to-digital converter (adc) successive approximation register (sar) pwm lpf fpga conversion
    Abstract: The flexibility provided by FPGAs permits the implementation of several ADCs, each one configured with the required bit resolution and sampling frequency. The paper presents the design and implementation of scalable and parametrizable analog-to-digital converters (ADC), based on a successive approximation register (SAR), on FPGAs (field programmable gate arrays). Firstly, the work develops a systematic methodology for the implementation of a parametrizable SAR-based ADC from a set of building modules, such as the pulse-width modulator (PWM), external low-pass filter (LPF) and the analog comparator. The presented method allows choosing the LPF parameters for the required performance (resolution bits and sampling frequency) of a SAR-based ADC. Secondly, the paper also presents several optimizations on the PWM module to enhance the sampling frequency of implemented ADCs, and the method to choose the LPF parameters is adapted. The PWM and SAR logic are synthesizable and parametrizable, using a low number of resources, in order to be portable for low-cost FPGA families. The methodology and PWM optimizations are tested on a Zynq-7000 device from Xilinx; however, they can be adapted to any other FPGA.
    Thematic Areas: Signal processing Physics, applied Hardware and architecture Engineering, electrical & electronic Engenharias iv Electrical and electronic engineering Control and systems engineering Computer science, information systems Computer networks and communications
    licence for use: https://creativecommons.org/licenses/by/3.0/es/
    Author's mail: juandavid.espitia@estudiants.urv.cat enric.vidal@urv.cat enrique.canto@urv.cat
    Author identifier: 0000-0002-6016-4096 0000-0002-5674-4119
    Record's date: 2024-07-20
    Papper version: info:eu-repo/semantics/publishedVersion
    Link to the original source: https://www.mdpi.com/2079-9292/11/3/447
    Licence document URL: http://repositori.urv.cat/ca/proteccio-de-dades/
    Papper original source: Electronics. 11 (3):
    APA: Espitia Castillo JD; Cantó Navarro E; Vidal-Idiarte E (2022). Design and Implementation of Scalable and Parametrizable Analog-to-Digital Converter on FPGA. Electronics, 11(3), -. DOI: 10.3390/electronics11030447
    Article's DOI: 10.3390/electronics11030447
    Entity: Universitat Rovira i Virgili
    Journal publication year: 2022
    Publication Type: Journal Publications
  • Keywords:

    Computer Networks and Communications,Computer Science, Information Systems,Control and Systems Engineering,Electrical and Electronic Engineering,Engineering, Electrical & Electronic,Hardware and Architecture,Physics, Applied,Signal Processing
    Successive approximation register (sar)
    Pwm
    Lpf
    Interleaved sar adc
    Fpga
    Analog-to-digital converter (adc)
    successive approximation register (sar)
    pwm
    lpf
    fpga
    conversion
    Signal processing
    Physics, applied
    Hardware and architecture
    Engineering, electrical & electronic
    Engenharias iv
    Electrical and electronic engineering
    Control and systems engineering
    Computer science, information systems
    Computer networks and communications
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