Articles producció científica> Enginyeria Electrònica, Elèctrica i Automàtica

Hardware-software co-design of an iris recognition algorithm

  • Identification data

    Identifier: imarina:9285081
    Handle: https://hdl.handle.net/20.500.11797/imarina9285081
    Authors:
    López MDaugman JCantó E
    Abstract:
    This study describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32-bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algorithm has been implemented on a low-cost Spartan 3 FPGA, achieving significant reduction in execution time when compared with a conventional software-based application. Experimental results show that with a clock speed of 40MHz, an IrisCode is obtained in <523ms from an image of 640×480 pixels, which is just 20 of the total time needed by a software solution running on the same microprocessor embedded in the architecture. © 2011 The Institution of Engineering and Technology.

  • Others:

    Author, as appears in the article.: López M; Daugman J; Cantó E
    Department: Enginyeria Electrònica, Elèctrica i Automàtica
    URV's Author/s: Cantó Navarro, Enrique Fernando
    Keywords: System architectures Spartan-3 Software-based Software solution Microprocessor chips Iris recognition algorithm Hardware software codesign Execution time Embedded software Co-processors Clock speed Biometrics Algorithms
    Abstract: This study describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32-bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algorithm has been implemented on a low-cost Spartan 3 FPGA, achieving significant reduction in execution time when compared with a conventional software-based application. Experimental results show that with a clock speed of 40MHz, an IrisCode is obtained in <523ms from an image of 640×480 pixels, which is just 20 of the total time needed by a software solution running on the same microprocessor embedded in the architecture. © 2011 The Institution of Engineering and Technology.
    Thematic Areas: Software Information systems Engenharias iv Computer science, theory & methods Computer science, information systems Computer networks and communications
    licence for use: https://creativecommons.org/licenses/by/3.0/es/
    Author's mail: enrique.canto@urv.cat
    Author identifier: 0000-0002-5674-4119
    Record's date: 2023-02-23
    Papper version: info:eu-repo/semantics/submittedVersion
    Link to the original source: https://digital-library.theiet.org/content/journals/10.1049/iet-ifs.2009.0267
    Papper original source: Iet Information Security. 5 (1): 60-68
    APA: López M; Daugman J; Cantó E (2011). Hardware-software co-design of an iris recognition algorithm. Iet Information Security, 5(1), 60-68. DOI: 10.1049/iet-ifs.2009.0267
    Licence document URL: https://repositori.urv.cat/ca/proteccio-de-dades/
    Article's DOI: 10.1049/iet-ifs.2009.0267
    Entity: Universitat Rovira i Virgili
    Journal publication year: 2011
    Publication Type: Journal Publications

  • Keywords:

    Computer Networks and Communications,Computer Science, Information Systems,Computer Science, Theory & Methods,Information Systems,Software
    System architectures
    Spartan-3
    Software-based
    Software solution
    Microprocessor chips
    Iris recognition algorithm
    Hardware software codesign
    Execution time
    Embedded software
    Co-processors
    Clock speed
    Biometrics
    Algorithms
    Software
    Information systems
    Engenharias iv
    Computer science, theory & methods
    Computer science, information systems
    Computer networks and communications

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