Author, as appears in the article.: Canto-Navarro E; Lopez-Garcia M; Ramos-Lara R; Sanchez-Reillo R
Department: Enginyeria Electrònica, Elèctrica i Automàtica
URV's Author/s: Cantó Navarro, Enrique Fernando
Keywords: Verification systems Verification process Verification algorithms User requirements System-on-chip Speech recognition Speaker recognition Number of clock cycles Hardware-software codesign Floating point units Floating point operations Field-programmable gate arrays (fpgas) Field programmable gate arrays (fpga) Environmental conditions Digital arithmetic Clocks Biometrics Arm processors Algorithms
Abstract: This paper presents the implementation of a speaker-verification system on field programmable gate array. The algorithm is executed by software over an embedded system that includes a MicroBlaze microprocessor connected to a vector floating-point unit (VFPU). The VFPU is designed to speed up the resolution of any vector floating-point operation involved in the verification algorithm, whereas the microprocessor manages the control of the process and executes the rest of operations. With a clock frequency of 40 MHz, the system is capable of executing the complete algorithm in real time, processing a voice frame in 9.1 ms. The same verification process was carried out for two different systems: 1) an ARM Cortex A8 microprocessor; and 2) configuring MicroBlaze with the scalar floating-point unit provided by Xilinx. The experimental results show that when comparing our proposed system against both systems, the number of clock cycles is reduced by a factor of 11.2 &Times; and 15.4 &Times;, respectively. The main advantage of the VFPU is its flexibility, which allows quick adaptation of the software to the potential changes produced in both the system and the user requirements. The algorithm was tested over a public database that contains the utterances of different users acquired under different environmental conditions, providing good recognition rates. © 2014 IEEE.
Thematic Areas: Software Hardware and architecture Engineering, electrical & electronic Engenharias iv Electrical and electronic engineering Computer science, hardware & architecture Ciência da computação
licence for use: https://creativecommons.org/licenses/by/3.0/es/
Author's mail: enrique.canto@urv.cat
Author identifier: 0000-0002-5674-4119
Record's date: 2024-09-07
Papper version: info:eu-repo/semantics/acceptedVersion
Link to the original source: https://ieeexplore.ieee.org/document/6996050
Licence document URL: https://repositori.urv.cat/ca/proteccio-de-dades/
Papper original source: Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23 (11): 2497-2507
APA: Canto-Navarro E; Lopez-Garcia M; Ramos-Lara R; Sanchez-Reillo R (2015). Flexible Biometric Online Speaker-Verification System Implemented on FPGA Using Vector Floating-Point Units. Ieee Transactions On Very Large Scale Integration (Vlsi) Systems, 23(11), 2497-2507. DOI: 10.1109/TVLSI.2014.2377578
Article's DOI: 10.1109/TVLSI.2014.2377578
Entity: Universitat Rovira i Virgili
Journal publication year: 2015
Publication Type: Journal Publications
Repositori URV