Articles producció científica> Enginyeria Electrònica, Elèctrica i Automàtica

Hardware architecture implemented on FPGA for protecting cryptographic keys against side-channel attacks

  • Datos identificativos

    Identificador: imarina:5131655
    Autores:
    Lumbiarres-Lopez, RubenLopez-Garcia, MarianoCanto-Navarro, Enrique
    Resumen:
    This paper presents a new hardware architecture designed for protecting the key of cryptographic algorithms against attacks by side-channel analysis (SCA). Unlike previous approaches already published, the fortress of the proposed architecture is based on revealing a false key. Such a false key is obtained when the leakage information, related to either the power consumption or the electromagnetic radiation (EM) emitted by the hardware device, is analysed by means of a classical statistical method. In fact, the trace of power consumption (or the EM) does not reveal any significant sign of protection in its behaviour or shape. Experimental results were obtained by using a Virtex 5 FPGA, on which a 128-bit version of the standard AES encryption algorithm was implemented. The architecture could easily be extrapolated to an ASIC device based on standard cell libraries. The system is capable of concealing the real key when various attacks are performed on the AES algorithm, using two statistical methods which are based on correlation, the Welch's t-test and the difference of means.
  • Otros:

    Autor según el artículo: Lumbiarres-Lopez, Ruben; Lopez-Garcia, Mariano; Canto-Navarro, Enrique;
    Departamento: Enginyeria Electrònica, Elèctrica i Automàtica
    Autor/es de la URV: Cantó Navarro, Enrique Fernando
    Palabras clave: Software-hardware countermeasures Side-channel attacks Security Power analysis attacks
    Resumen: This paper presents a new hardware architecture designed for protecting the key of cryptographic algorithms against attacks by side-channel analysis (SCA). Unlike previous approaches already published, the fortress of the proposed architecture is based on revealing a false key. Such a false key is obtained when the leakage information, related to either the power consumption or the electromagnetic radiation (EM) emitted by the hardware device, is analysed by means of a classical statistical method. In fact, the trace of power consumption (or the EM) does not reveal any significant sign of protection in its behaviour or shape. Experimental results were obtained by using a Virtex 5 FPGA, on which a 128-bit version of the standard AES encryption algorithm was implemented. The architecture could easily be extrapolated to an ASIC device based on standard cell libraries. The system is capable of concealing the real key when various attacks are performed on the AES algorithm, using two statistical methods which are based on correlation, the Welch's t-test and the difference of means.
    Áreas temáticas: General computer science Engenharias iv Engenharias iii Electrical and electronic engineering Computer science, software engineering Computer science, information systems Computer science, hardware & architecture Computer science (miscellaneous) Computer science (all) Ciência da computação
    Acceso a la licencia de uso: https://creativecommons.org/licenses/by/3.0/es/
    Direcció de correo del autor: enrique.canto@urv.cat
    Identificador del autor: 0000-0002-5674-4119
    Fecha de alta del registro: 2024-09-07
    Versión del articulo depositado: info:eu-repo/semantics/acceptedVersion
    Enlace a la fuente original: https://ieeexplore.ieee.org/document/7571149
    URL Documento de licencia: https://repositori.urv.cat/ca/proteccio-de-dades/
    Referencia al articulo segun fuente origial: Ieee Transactions On Dependable And Secure Computing. 15 (5): 898-905
    Referencia de l'ítem segons les normes APA: Lumbiarres-Lopez, Ruben; Lopez-Garcia, Mariano; Canto-Navarro, Enrique; (2018). Hardware architecture implemented on FPGA for protecting cryptographic keys against side-channel attacks. Ieee Transactions On Dependable And Secure Computing, 15(5), 898-905. DOI: 10.1109/TDSC.2016.2610966
    DOI del artículo: 10.1109/TDSC.2016.2610966
    Entidad: Universitat Rovira i Virgili
    Año de publicación de la revista: 2018
    Tipo de publicación: Journal Publications
  • Palabras clave:

    Computer Science (Miscellaneous),Computer Science, Hardware & Architecture,Computer Science, Information Systems,Computer Science, Software Engineering,Electrical and Electronic Engineering
    Software-hardware countermeasures
    Side-channel attacks
    Security
    Power analysis attacks
    General computer science
    Engenharias iv
    Engenharias iii
    Electrical and electronic engineering
    Computer science, software engineering
    Computer science, information systems
    Computer science, hardware & architecture
    Computer science (miscellaneous)
    Computer science (all)
    Ciência da computação
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