Autor según el artículo: Ribes-González J; Farràs O; Hernández C; Kostalabros V; Moretó M
Departamento: Enginyeria Informàtica i Matemàtiques
Autor/es de la URV: Farràs Ventura, Oriol / Ribes Gonzalez, Jordi
Palabras clave: Timing attacks Security definition Randomly-mapped caches Randomization-based protected caches Pseudo-random functions Cache side-channel attacks
Resumen: Cache side-channel attacks allow adversaries to learn sensitive information about co-running processes by using only access latency measures and cache contention. This vulnerability has been shown to lead to several microarchitectural attacks. As a promising solution, recent work proposes Randomization-based Protected Caches (RPCs). RPCs randomize cache addresses, changing keys periodically so as to avoid long-term leakage. Unfortunately, recent attacks have called the security of state-of-the-art RPCs into question. In this work, we tackle the problem of formally defining and analyzing the security properties of RPCs. We first give security definitions against access-based cache side-channel attacks that capture security against known attacks such as Prime+Probe and Evict+Probe. Then, using these definitions, we obtain results that allow to guarantee security by adequately choosing the rekeying period, the key generation algorithm and the cache randomizer, thus providing security proofs for RPCs under certain assumptions.
Áreas temáticas: Software Signal processing Hardware and architecture Computer networks and communications Computer graphics and computer-aided design Artificial intelligence
Acceso a la licencia de uso: https://creativecommons.org/licenses/by/3.0/es/
Direcció de correo del autor: oriol.farras@urv.cat
Identificador del autor: 0000-0002-7495-5980
Fecha de alta del registro: 2024-09-07
Versión del articulo depositado: info:eu-repo/semantics/publishedVersion
URL Documento de licencia: https://repositori.urv.cat/ca/proteccio-de-dades/
Referencia al articulo segun fuente origial: Iacr Transactions On Cryptographic Hardware And Embedded Systems. 2022 (3): 1-25
Referencia de l'ítem segons les normes APA: Ribes-González J; Farràs O; Hernández C; Kostalabros V; Moretó M (2022). A Security Model for Randomization-based Protected Caches. Iacr Transactions On Cryptographic Hardware And Embedded Systems, 2022(3), 1-25. DOI: 10.46586/tches.v2022.i3.1-25
Entidad: Universitat Rovira i Virgili
Año de publicación de la revista: 2022
Tipo de publicación: Journal Publications