A Novel PV Microinverter With Submodule-Level Balancing and Active Power Decoupling

Identificador:  imarina:9466972

Handle: https://hdl.handle.net/20.500.11797/imarina9466972

Autores:  Ahmad, U; Giral, R; Olalla, C; Blaabjerg, F

Resumen:
Conventional photovoltaic (PV) systems suffer from mismatch losses at the PV submodule level, which reduce energy yield and create hot spots. Hence, the reliability and lifetime of both the PV module and the microinverter are critical for the commercial viability of residential systems. To improve the reliability and longevity of both, this article proposes a novel PV microinverter architecture that integrates a series-stacked buffer converter (SSBC) for active power decoupling (APD) at the dc bus level and submodule-integrated converters (subMICs) for mismatch mitigation at the submodule level. Although the SSBC has previously been used for APD in the literature, it typically requires a dedicated input energy storage capacitor and a corresponding voltage regulation loop. Also, it demands additional sensors compared to other APD circuits, increasing system cost and complexity. The novel integration of the SSBC and subMICs in a two-stage microinverter brings three main advantages. First, the isolated-port capacitor of the subMICs, originally used for power balancing, is repurposed as the input energy storage for the SSBC, eliminating a redundant capacitor. Second, because the isolated port is well regulated by the subMICs, the need for a separate SSBC control loop is removed, simplifying and enhancing control robustness. Third, the isolated-port voltage can be adjusted according to the PV module's power level, optimizing SSBC efficiency under varying conditions. This article focuses on the modeling and control of the integrated power stages, with emphasis on simplifying SSBC control. The proposed concept has been validated experimentally with a 300-W microinverter prototype connected to a 180-W, 72-cell commercial PV module. The proposed approach has achieved a 1.2% voltage ripple on the dc bus with a 20- mu F film capacitor.