Diseño e implementación de un conversor analógico digital escalable y parametrizable en una FPGA

Identificador:  TDX:3978

Handle: https://hdl.handle.net/20.500.11797/TDX3978

Autores:  Espitia Castillo, Juan David

Resumen:
The flexibility provided by FPGAs permits the implementation of several Analog-to-Digital Converters (ADC), each one configured with the bit resolution and the sampling frequency required by the target application. The doctoral thesis presents two designs for the implementation of scalable and parametrizable N-bit ADC on FPGAs (Field Programmable Gate Arrays). The first design based on one shot circuit and the second design is based on a SAR (Successive Approximation Register). The first design is N-bit ADC based on the one-shot circuit. Combining a RC circuit and logic gates the ADC is implemented. A methodology for the implementation of a parametrizable one shot-based ADC is presented. Based on the sampling frequency, input voltage range and resolution the parameters for the implementation are found. The oneshot logic is synthesizable and parametrizable, using a low number of resources, to be portable to low-cost FPGA families.