Gate Length-Dependent Thermal Impedance Characterization of PD-SOI MOSFETs

Identifier:  imarina:9241949

Handle: https://hdl.handle.net/20.500.11797/imarina9241949

Authors:  Gonzalez, B; Cabrera, JM; Lazaro, A

Abstract:
Thermal impedance is required to describe static and fast dynamic thermal behavior in silicon-on-insulator (SOI) devices. This study presents an empirical physical model, which accounts for gate length, for calculating the thermal impedance of multi-finger partially depleted (PD) SOI MOSFETs at room temperature. For the first time, the parameters of the model are obtained from measurements of ac conductance and the characteristic thermal frequency determination. The model shows decreasing thermal resistance and linearly augmented thermal capacitance with increasing gate length from 0.18 to 2.50 mu m. Thus, thermal time constants of similar to 760 ns, extracted from a variety of gate lengths, are correctly predicted.