Autor según el artículo: Gonzalez, Benito; Cabrera, Jose M.; Lazaro, Antonio;
Departamento: Enginyeria Electrònica, Elèctrica i Automàtica
Autor/es de la URV: Lázaro Guillén, Antonio Ramon
Palabras clave: Thermal resistance Thermal impedance. Thermal impedance Thermal conductivity Temperature measurement Silicon-on-insulator mosfets Silicon-on-insulator (soi) mosfet Silicon on insulator technology Semiconductor device models Semiconductor device modeling Resistance Partially depleted silicon-on-insulator Mosfets Mosfet devices Mosfet Mos-fet Model Logic gates Impedance characterization Impedance Heat resistance Gate-length Extraction Electrothermal characterization model Electrothermal characterization Capacitance
Resumen: Thermal impedance is required to describe static and fast dynamic thermal behavior in silicon-on-insulator (SOI) devices. This study presents an empirical physical model, which accounts for gate length, for calculating the thermal impedance of multi-finger partially depleted (PD) SOI MOSFETs at room temperature. For the first time, the parameters of the model are obtained from measurements of ac conductance and the characteristic thermal frequency determination. The model shows decreasing thermal resistance and linearly augmented thermal capacitance with increasing gate length from 0.18 to 2.50 mu m. Thus, thermal time constants of similar to 760 ns, extracted from a variety of gate lengths, are correctly predicted.
Áreas temáticas: Physics, applied Materiais Interdisciplinar Engineering, electrical & electronic Engenharias iv Engenharias ii Electronic, optical and magnetic materials Electrical and electronic engineering Ciência da computação Astronomia / física
Acceso a la licencia de uso: https://creativecommons.org/licenses/by/3.0/es/
Direcció de correo del autor: antonioramon.lazaro@urv.cat
Identificador del autor: 0000-0003-3160-5777
Fecha de alta del registro: 2024-09-07
Versión del articulo depositado: info:eu-repo/semantics/acceptedVersion
Enlace a la fuente original: https://ieeexplore.ieee.org/document/9648224
URL Documento de licencia: https://repositori.urv.cat/ca/proteccio-de-dades/
Referencia al articulo segun fuente origial: Ieee Transactions On Electron Devices. 69 (2): 469-474
Referencia de l'ítem segons les normes APA: Gonzalez, Benito; Cabrera, Jose M.; Lazaro, Antonio; (2022). Gate Length-Dependent Thermal Impedance Characterization of PD-SOI MOSFETs. Ieee Transactions On Electron Devices, 69(2), 469-474. DOI: 10.1109/ted.2021.3132854
DOI del artículo: 10.1109/ted.2021.3132854
Entidad: Universitat Rovira i Virgili
Año de publicación de la revista: 2022
Tipo de publicación: Journal Publications
Repositori URV